Priyal Chhatrapati

	Machine Learning Performance Engineer \|Apple Dec'22 - Present Developing Machine Learning Inference stack for Apple Devices.
	Deep Learning Performance Intern \|NVIDIA May'22 - Aug'22 Working in the MLPerf TensorRT team to optimize Deep Learning Inference on NVIDIA GPU chips.
	Graduate Research Assistant \|Georgia Institute of Technology August'21 - May'22 Working with Prof. Callie Hao at the Department of Electrical and Computer Engineering at Georgia Tech. We work on accelerating Computer Vision Workloads using Hardware.
	ASIC Design Engineer \| Sifive September '20 - June '21 Worked on functional Verification and RTL design for building the next generation of RISC-V enabled Microprocessors.
	Intern \| National University of Singapore Aug '19 - Dec '19 Worked with Prof. Djordje Jevdjic at the School of Computing at National University of Singapore. We built an approximate storage framework for images and videos for the DNA Data Storage paradigm.
	Summer Intern \| Shakti Microprocessor Group May '19 - June '19 Worked under the supervision of Prof. V. Kamakoti at Shakti Processor Group, IIT, Madras. We built a CNN Inference accelerator which used a systolic array architecture to reduce the compute time of Convolutions.
	Summer Intern \| Indira Gandhi Centre for Atomic Research May '18 - July '18 Worked with the Security and Innovation Sensors Division to dvelop an embedded system around the quasi digital sensors to measure, control and transmit the density and turbidity of a fluid.

	Trace Based L1 cache simulator A trace-based simulator is one that consumes a file of load-store instructions and uses that information to fuel a simulation by calculating metrics like miss rate. My C++ implementation is reconfigurable and accepts cache capacity, blocksize and associativity as command line arguements. It uses a write back policy for write hits, write allocate policy for write misses and a LRU replacement policy for eviction.
	MIPS In order Processor Github repo A 4 staged 8 bit MIPS ISA based processor implemented in Verilog. The processor has 8 registers (R0-R7). It supports addition, jump and unconditional jump operations. It resolves data hazards using forwarding and control hazards by flushing the pipeline.
	Dead Drop Evil Chat Client Github repo Chat Client where the reciever process uses the Flush Reload attack to spy on the sender process to extract the message. Flush Reload is a Side channel attack on the Last Level of the Cache. The sender and receiver donot share any memory or use any IPC and sockets to communicate with each other. The "Evil" chat client breaks process isolation provided by the Operating System.
	Arcade Game using STM32F407IG Video Fun Math game for elementary school students using an STM32 evaluation board, a keypad and a display. Asks random arithmetic questions using RTC, increasing the difficulty overtime.
	Home Automation using Arduino Arduino controlling the light and fan speed based on input from the temperature sensor and light sensor. Manual control using switches and pot interfaced with Arduino and/or through a website.