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Priyal Chhatrapati

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I am Priyal Chhatrapati, an MS student at Georgia Tech starting from Fall 2021. Currently, I work at NVIDIA as a Deep Learning Performance intern as a part of the MLPerf, TensorRT team. I help them with the biannual MLPerf inference submission.

During the course of my Master's degree, I worked with Prof Callie Hao on acceleration of Computer Vision/ Deep learning models (Object Tracking) using FPGAs. My worked involved optimizing the software stack for Deep Learing(Pytorch) for FPGAs. Before that, I worked at Sifive in the FPGA team. I completed my undergraduate degree with distinction at BITS, Pilani where I majored in Electronics and Instrumentation Engineering. I am interested in the intersection of Computer Architecture, Embedded Systems and Artificial Intelligence. More recently, I have been exploring the new verticals like Hardware Security and DNA based Storage.

During the final year of my undergrad, I spent six wonderful months with Prof Djordje Jevdjic at NUS working on Approximate DNA Storage. And in the preceeding summer, I interned with Shakti Processor group at Indian Institute of Technology, Madras where we made a Machine Learning Accelerator for the Shakti processor enivonment.

I am an ardent sports fan and I follow Manchester United (Football/soccer), LA Rams (American Football), Dodgers and Braves (Baseball(MLB)), Golden State Warriors (Basketball(NBA)) and McLaren (Formula 1). I was fortunate enough to attend Austin Grand Prix, 2021 and get a Bay Grandstand seat for the Singapore Grand Prix, 2019. I am love with Japanese Anime. Some of my favorites are One Piece, Demon Slayer and Cowboy Bebop.

Feel free to check out my CV and drop me an e-mail if you want to chat with me!

 ~  Email  |  CV  |  Github  |  Linkedin  |  Twitter  ~ 


[May '21]  

Started Internship at NVIDIA

[Aug '21]  

Started MS degree in ECE at Georgia Tech

[June '21]  

Last day at Sifive as a ASIC Design Engineer

[Aug '20]  

Started working with Sifive as a ASIC Design Engineer

[Aug '20]  

Graduated From BITS Pilani with Distinction

[Jan '20]  

Returned to BITS Pilani for Final Semester

[Aug '19]  

Started working with Prof. Djordje Jevdjic at NUS for my bachelor's thesis

[May '19]    

Started working at Shakti Processor Group as a Summer Intern

[Aug '18]    

Returned to BITS Pilani for Pre-Final Year

[May '18]    

Started working at IGCAR as Summer Intern

Deep Learning Performance Intern |NVIDIA
May'22 - present

Working in the MLPerf TensorRT team to optimize Deep Learning Inference on NVIDIA GPU chips.

Graduate Research Assistant |Georgia Institute of Technology
August'21 - May'22

Working with Prof. Callie Hao at the Department of Electrical and Computer Engineering at Georgia Tech. We work on accelerating Computer Vision Workloads using Hardware.

ASIC Design Engineer | Sifive
September '20 - June '21

Worked on functional Verification and RTL design for building the next generation of RISC-V enabled Microprocessors.

Intern | National University of Singapore
Aug '19 - Dec '19

Worked with Prof. Djordje Jevdjic at the School of Computing at National University of Singapore. We built an approximate storage framework for images and videos for the DNA Data Storage paradigm.

Summer Intern | Shakti Microprocessor Group
May '19 - June '19

Worked under the supervision of Prof. V. Kamakoti at Shakti Processor Group, IIT, Madras. We built a CNN Inference accelerator which used a systolic array architecture to reduce the compute time of Convolutions.

Summer Intern | Indira Gandhi Centre for Atomic Research
May '18 - July '18

Worked with the Security and Innovation Sensors Division to dvelop an embedded system around the quasi digital sensors to measure, control and transmit the density and turbidity of a fluid.


Trace Based L1 cache simulator
Trace Based L1 cache simulator

A trace-based simulator is one that consumes a file of load-store instructions and uses that information to fuel a simulation by calculating metrics like miss rate. My C++ implementation is reconfigurable and accepts cache capacity, blocksize and associativity as command line arguements. It uses a write back policy for write hits, write allocate policy for write misses and a LRU replacement policy for eviction.

MIPS Pipeline
MIPS In order Processor

Github repo

A 4 staged 8 bit MIPS ISA based processor implemented in Verilog. The processor has 8 registers (R0-R7). It supports addition, jump and unconditional jump operations. It resolves data hazards using forwarding and control hazards by flushing the pipeline.

Dead Drop Chat Cliet Flush Reload
Dead Drop Evil Chat Client

Github repo

Chat Client where the reciever process uses the Flush Reload attack to spy on the sender process to extract the message. Flush Reload is a Side channel attack on the Last Level of the Cache. The sender and receiver donot share any memory or use any IPC and sockets to communicate with each other. The "Evil" chat client breaks process isolation provided by the Operating System.

Math Test using STM32F407IG
Arcade Game using STM32F407IG

Video

Fun Math game for elementary school students using an STM32 evaluation board, a keypad and a display. Asks random arithmetic questions using RTC, increasing the difficulty overtime.

Home Automation using Arduino Uno
Home Automation using Arduino

Arduino controlling the light and fan speed based on input from the temperature sensor and light sensor. Manual control using switches and pot interfaced with Arduino and/or through a website.


This website is a modification of Jon Barron's website. Find the source code to my website here.